#ifndef __ASM_ARCH_WS_H
#define __ASM_ARCH_WS_H

#include <linux/init.h>
#include <mach/io.h>

#define SRAM_GRANULARITY		32
#define SRAM_SIZE			(SZ_512K+SZ_128K)

#define RAM_BASE			(0x00100000)
#define DDR_BASE			(0x40000000)
#define GICD_REG_BASE		(GIC_REG_BASE+0x1000)
#define GICC_REG_BASE		(GIC_REG_BASE+0x2000)

#define GIC_REG_BASE			(0x00200000)
#define CPU_MTX_APB_REG_BASE	(0x0b200000)
#define CPU_SYS_AHB_REG_BASE	(0x0c000000)

#define DMA0_REG_BASE			(0x0c700000)
#define C2C_INTR0_REG_BASE		(0x0a100000)
#define C2C_INTR1_REG_BASE		(0x0a200000)
#define UART0_REG_BASE			(0x08f00000)
#define UART1_REG_BASE			(0x09000000)
#define UART2_REG_BASE			(0x09100000)
#define I2C0_REG_BASE			(0x08d00000)
#define I2C1_REG_BASE			(0x08e00000)
#define I2S_REG_BASE			(0x08900000)
#define RTC_REG_BASE			(0x2c900000)
#define TOP_PRE_DIV_RF_REG_BASE	(0x10300000)
#define TOP_CLK_RF_REG_BASE		(0x10300200)
#define TOP_CLK_GATE_RF_REG_BASE (0x10300400)
#define TIMER0_REG_BASE			(0x09800000)
#define SYS_TIMER_REG_BASE		(0x09700000)
#define WDT0_REG_BASE			(0x09600000)
#define GPIO0_REG_BASE			(0x0B000000)
#define GPIO1_REG_BASE			(0x0B010000)
#define GPIO2_REG_BASE			(0x0B020000)
#define GPIO3_REG_BASE			(0x0B030000)
#define GPIO4_REG_BASE			(0x0B040000)
#define GPIO5_REG_BASE			(0x0B050000)
#define GPIO6_REG_BASE			(0x0B060000)
#define SPI1_REG_BASE			(0x08b00000)
#define SPI0_REG_BASE			(0x08c00000)
#define INT_CTRL0_REG_BASE		(0x09f00000)
#define INT_CTRL1_REG_BASE		(0x0a000000)
#define PWM_REG_BASE			(0x09500000)
#define CEN_GLB_APB_REG_BASE	(0x10000000)
#define PMU_CFG_REG_BASE		(0x10100000)
#define CEN_PIN_REG_BASE		(0x10200000)
#define GMAC0_REG_BASE			(0x1c600000)

#define SADC_REG_BASE			(0x1c500000)
#define ACW_REG_BASE			(0x24A00000)
#define EFUSE_REG_BASE			(0x0A700000)
#define AES_REG_BASE			(0x0C600000)
#define SDIO1_REG_BASE			(0x2D200000)
#define DMC_SYS_APB_REG_BASE	(0x24000000)
#define DDR_CTRL_REG_BASE		(0x24100000)
#define DDR_PHY_REG_BASE		(0x24200000)
#define DFI_MON_REG_BASE		(0x2C400000)
#define DDR_FW_REG_BASE			(0x2C500000)
#define PERF_MON0_REG_BASE		(0x24800000)
#define PERF_MON1_REG_BASE		(0x24900000)
#define PERF_MON2_REG_BASE		(0x24a00000)
#define EPHY_REG_BASE			(0x1c900000)

#define VEU_SYS_PIN_REG_BASE	(0x1c100000)
#define ISP_SYS_PIN_REG_BASE	(0x2c000000)
#define CSI_SYS_PIN_REG_BASE	(0x2c600000)
#define CPU_SYS_PIN_REG_BASE	(0x0b100000)

#define CPU_SYS_CLK_RF_PRE_REG_BASE	(0x09200000)

#define SFC_REG_BASE			(0x30800000)

#define SDIO0_REG_BASE			(0x2D100000)
#define USB_PHY_REG_BASE		(0x1CA00000)
#define USBC_REG_BASE			(0x1D100000)
#define VEU_SYS_AHB_REG_BASE	(0x1c000000)
#define ISP_SYS_APB_REG_BASE	(0x2c100000)
#define PTS_REG_BASE			(0x2c300000)
#define STM0_REG_BASE                   (0x0A400000)
#define STM1_REG_BASE                   (0x0A800000)


/* sys reg io maps */
#define SYS_REG_V2P(va)		((((va)&0x00ffc000)<<6)+((va)&0x3fff))
#define SYS_REG_P2V_OFF(pa) ((((pa)>>6) & (0x00ffc000)) | ((pa)&0x3fff))
#define SYS_REG_P2V(pa)		(VA_SYS_REG_BASE+SYS_REG_P2V_OFF(pa))
#define VA_SYS_REG_BASE		(0xFD000000)

#define VA_CPU_SYS_AHB_REG_BASE		(SYS_REG_P2V(CPU_SYS_AHB_REG_BASE))
#define VA_TOP_PRE_DIV_RF_REG_BASE	(SYS_REG_P2V(TOP_PRE_DIV_RF_REG_BASE))
#define VA_CEN_GLB_APB_REG_BASE		(SYS_REG_P2V(CEN_GLB_APB_REG_BASE))
#define VA_PTS_REG_BASE				(SYS_REG_P2V(PTS_REG_BASE))
#define VA_DMC_SYS_APB_REG_BASE		(SYS_REG_P2V(DMC_SYS_APB_REG_BASE))
#define VA_VEU_SYS_AHB_REG_BASE		(SYS_REG_P2V(VEU_SYS_AHB_REG_BASE))
#define VA_ISP_SYS_APB_REG_BASE		(SYS_REG_P2V(ISP_SYS_APB_REG_BASE))
#define VA_CPU_SYS_CLK_RF_PRE_REG_BASE	\
				(SYS_REG_P2V(CPU_SYS_CLK_RF_PRE_REG_BASE))
#define VA_CPU_SYS_CLK_RF_REG_BASE	(VA_CPU_SYS_CLK_RF_PRE_REG_BASE + 0x200)

/* pin reg io maps */
#define VA_CEN_PIN_REG_BASE			(SYS_REG_P2V(CEN_PIN_REG_BASE))
#define VA_VEU_SYS_PIN_REG_BASE		(SYS_REG_P2V(VEU_SYS_PIN_REG_BASE))
#define VA_ISP_SYS_PIN_REG_BASE		(SYS_REG_P2V(ISP_SYS_PIN_REG_BASE))
#define VA_CSI_SYS_PIN_REG_BASE		(SYS_REG_P2V(CSI_SYS_PIN_REG_BASE))
#define VA_CPU_SYS_PIN_REG_BASE		(SYS_REG_P2V(CPU_SYS_PIN_REG_BASE))

#define VA_TOP_CLK_RF_REG_BASE		(VA_TOP_PRE_DIV_RF_REG_BASE + 0x200)
#define VA_TOP_CLK_GATE_RF_REG_BASE	(VA_TOP_PRE_DIV_RF_REG_BASE + 0x400)

#define VA_PMU_CFG_REG_BASE			(SYS_REG_P2V(PMU_CFG_REG_BASE))
#define REG_PMU_ECO0				(VA_PMU_CFG_REG_BASE + 0x32c)

#define INT_CTRL3_SOFT_RST		27
#define INT_CTRL2_SOFT_RST		26
#define MOTORCTL1_DB_SOFT_RST	25
#define MOTORCTL1_SOFT_RST		24
#define MOTORCTL0_DB_SOFT_RST	23
#define MOTORCTL0_SOFT_RST		22
#define SPIC_SOFT_RST			21
#define SPIC_APB_SOFT_RST		20
#define TIMER0_RTC_SOFT_RST		19
#define TIMER0_XTL_SOFT_RST		18
#define PWM_SOFT_RST			17
#define SYST_SOFT_RST			16
#define SPI0_SOFT_RST			15
#define WDT_SOFT_RST			14
#define I2S0_SOFT_RST			13
#define I2C1_SOFT_RST			12
#define I2C0_SOFT_RST			11
#define C2C_CA7_TO_ARC_SOFT_RST	10
#define C2C_ARC_TO_CA7_SOFT_RST	9
#define EFUSE_SOFT_RST			8
#define ARC_TS_24M_SOFT_RST		7
#define UART1_SOFT_RST			6
#define UART0_SOFT_RST			5
#define INT_CTRL1_SOFT_RST		3
#define INT_CTRL0_SOFT_RST		2
#define AHB_HSLOCK_SOFT_RST		1
#define ADDRMON_ARC_SOFT_RST	0

#define REG_IIS0_CLK_CTRL	(SYS_REG_P2V_OFF(CPU_SYS_AHB_REG_BASE) + 0xB8)

/* CPU_SYS_AHB_REG_BASE */
#define REG_CPU_SYS_CLK_CTRL	(SYS_REG_P2V_OFF(CPU_SYS_AHB_REG_BASE) \
								+ 0x1C0)
#define REG_ARC600_0_CTRL		(SYS_REG_P2V_OFF(CPU_SYS_AHB_REG_BASE) \
								+ 0x1D0)
#define REG_CPU_SYS_MTX_CTRL0    (SYS_REG_P2V_OFF(CPU_SYS_AHB_REG_BASE) + 0x1CC)
#define CKG_ARC600_AUTO_GATE_SEL	(BIT(23))
#define ARC0_CTRL_CPU_START		(BIT(3))
#define ARC0_START_A			(BIT(2))
#define ARC600_0_EN				(BIT(1))
#define ARC_SOFT_RST			(BIT(0))

#define REG_EPHY_CTRL0		(SYS_REG_P2V_OFF(CPU_SYS_AHB_REG_BASE) \
								+ 0x1FC)
#define REG_GMAC_CTRL0		(SYS_REG_P2V_OFF(CPU_SYS_AHB_REG_BASE) \
								+ 0x1DC)

/* TOP_SYS_APB_REG_BASE */

#define REG_AP_PERI_SOFT_RST0	(SYS_REG_P2V_OFF(CPU_SYS_AHB_REG_BASE) + 0xb4)

#define CKG_I2S_FRAC_DIV_EN		BIT(4)
#define CKG_I2S_FAST_EN			BIT(3)
#define CKG_I2S_SOURCE_SEL		BIT(2)
#define CKG_I2S_REV				BIT(1)
#define I2S_MCLK_SEL			BIT(0)
#define REG_CKG_I2S_FRAC_DIV_M	(SYS_REG_P2V_OFF(CPU_SYS_AHB_REG_BASE) + 0xBC)
#define REG_CKG_I2S_FRAC_DIV_N	(SYS_REG_P2V_OFF(CPU_SYS_AHB_REG_BASE) + 0xC0)
#define REG_CKG_I2S0_CTL	(SYS_REG_P2V_OFF(CPU_SYS_AHB_REG_BASE) + 0xC4)

/* CEN_GLB_APB_REG_BASE */
#define REG_GLB_RESET		(SYS_REG_P2V_OFF(CEN_GLB_APB_REG_BASE) + 0x100)
#define SW_GLB_RST				(BIT(0))
#define SW_EXT_RST				(BIT(1))
#define REG_PKG_ID		(SYS_REG_P2V_OFF(CEN_GLB_APB_REG_BASE) + 0x500)

#define REG_WR_PROTECT		(SYS_REG_P2V_OFF(CEN_GLB_APB_REG_BASE) + 0x548)
#define REG_PMU_CHIP_ID		(SYS_REG_P2V_OFF(CEN_GLB_APB_REG_BASE) + 0x198)
#define REG_PMU_BOOT_MODE	(SYS_REG_P2V_OFF(CEN_GLB_APB_REG_BASE) + 0x0508)
#define REG_PMU_DDR_SIZE	(SYS_REG_P2V_OFF(CEN_GLB_APB_REG_BASE) + 0x050C)
#define REG_PMU_RESERVED2	(SYS_REG_P2V_OFF(CEN_GLB_APB_REG_BASE) + 0x0510)
#define REG_PMU_CHIP_INFO	(SYS_REG_P2V_OFF(CEN_GLB_APB_REG_BASE) + 0x0514)
#define REG_PMU_EPHY_PARAM	(SYS_REG_P2V_OFF(CEN_GLB_APB_REG_BASE) + 0x0518)
#define REG_PMU_RTC_PARAM	(SYS_REG_P2V_OFF(CEN_GLB_APB_REG_BASE) + 0x051c)
#define REG_ARC600_0_BOOT0	(SYS_REG_P2V_OFF(CEN_GLB_APB_REG_BASE) + 0x0)
#define REG_ARC600_0_BOOT1	(SYS_REG_P2V_OFF(CEN_GLB_APB_REG_BASE) + 0x4)
#define REG_ARC600_0_BOOT2	(SYS_REG_P2V_OFF(CEN_GLB_APB_REG_BASE) + 0x8)
#define REG_ARC600_0_BOOT3	(SYS_REG_P2V_OFF(CEN_GLB_APB_REG_BASE) + 0xC)






/* DMC_SYS_APB_REG_BASE */
#define REG_DFIMON_TMR1_CTRL0	(SYS_REG_P2V_OFF(DMC_SYS_APB_REG_BASE) + 0x0)
#define REG_DFIMON_TMR1_CTRL1	(SYS_REG_P2V_OFF(DMC_SYS_APB_REG_BASE) + 0x4)
#define REG_DFIMON_TMR1_CTRL2	(SYS_REG_P2V_OFF(DMC_SYS_APB_REG_BASE) + 0x8)
#define REG_HIGH_LEN_TIMER1	(REG_DFIMON_TMR1_CTRL1)
#define REG_LOW_LEN_TIMER1	(REG_DFIMON_TMR1_CTRL2)
#define REG_DMC_CLK_CTRL	(SYS_REG_P2V_OFF(DMC_SYS_APB_REG_BASE) + 0x300)
#define REG_PERF_TRIGGER	(SYS_REG_P2V_OFF(DMC_SYS_APB_REG_BASE) + 0xB04)



/* ISP_SYS_APB_REG_BASE */
#define REG_PTS_RD_LOW		(SYS_REG_P2V_OFF(ISP_SYS_APB_REG_BASE) + 0x7c)
#define REG_PTS_RD_HIGH		(SYS_REG_P2V_OFF(ISP_SYS_APB_REG_BASE) + 0x80)

#define REG_PTS_UPDATE		(SYS_REG_P2V_OFF(PTS_REG_BASE) + 0x0)

#define CONSOLE_REG_BASE		UART0_REG_BASE
#define FH_UART_NUMBER			3


#define SDIO0_CTRL0			(VA_ISP_SYS_APB_REG_BASE + 0x54)
#define SDIO0_CTRL1			(VA_ISP_SYS_APB_REG_BASE + 0x58)
#define SDIO0_DLLININFOREG_SPL		(VA_ISP_SYS_APB_REG_BASE + 0x60)

#define CK_CTRL2			(VA_ISP_SYS_APB_REG_BASE + 0x4)

#define SDIO1_CTRL0			(VA_ISP_SYS_APB_REG_BASE + 0x8c)
#define SDIO1_DLLININFOREG_SPL		(VA_ISP_SYS_APB_REG_BASE + 0x98)
#define SDIO1_CTRL1			(VA_ISP_SYS_APB_REG_BASE + 0x90)

#define RTC_IRQ				32
#define SDIO0_IRQ			35
#define ACODEC_IRQ			36
#define JPG_IRQ				37
#define VDEC_IRQ			38
#define USBC_IRQ			39
#define GMAC0_SBD_INTR_IRQ		40
#define GMAC0_SBD_PERCH_TX0_IRQ	41
#define GMAC0_SBD_PERCH_RX0_IRQ	42
#define NNA_IRQ				43
#define DFI_ALERT_ERR_IRQ	44
#define DFI_MON_IRQ			45
#define DMC_PORT_MPU_IRQ	46
#define DMC_PERF_MON_IRQ	47
#define DMC_PORT_POISON_IRQ	48
#define DDRPHY_IRQ			49
#define I2C0_IRQ			50
#define I2C1_IRQ			51
#define UART0_IRQ			52
#define UART1_IRQ			53
#define GPIO0_IRQ			54
#define GPIO1_IRQ			55
#define GPIO2_IRQ			56
#define GPIO3_IRQ			57
#define GPIO4_IRQ			58
#define GPIO5_IRQ			59
#define SPI1_IRQ			60
#define SPI0_IRQ			61
#define WDT0_IRQ			62
#define TIMER0_IRQ			64
#define TMR0_IRQ		(TIMER0_IRQ)
#define PWM_IRQ				65
#define STM0_IRQ			66
#define STM1_IRQ			67
#define DMA0_IRQ			68
#define AES_IRQ				69
#define ADDR_MON_CA7_IRQ	70
#define ARC_TO_CA7_COMBIRQ	71
#define I2S0_IRQ			72
#define ARC_TO_CA7_IRQ0		75
#define ARC_TO_CA7_IRQ1		76
#define ARC_TO_CA7_IRQ2		77
#define ARC_TO_CA7_IRQ3		78
#define ARC_TO_CA7_IRQ4		79
#define ARC_TO_CA7_IRQ5		80
#define ARC_TO_CA7_IRQ6		81
#define ARC_TO_CA7_IRQ7		82
#define ARC_TO_CA7_IRQ8		83
#define ARC_TO_CA7_IRQ9		84
#define UART2_IRQ			85
#define SDIO1_IRQ			87
#define SADC_IRQ			88
#define GPIO6_IRQ			89

#define MEM_START_PHY_ADDR	DDR_BASE
#define MEM_SIZE			0x10000000

/* FH Serial HardWare HandShake */
#define UART1_TX_HW_HANDSHAKE   (3)
#define UART1_RX_HW_HANDSHAKE   (2)
#define UART2_TX_HW_HANDSHAKE   (19)
#define UART2_RX_HW_HANDSHAKE   (18)
#define UART1_DMA_TX_CHAN       (0)
#define UART1_DMA_RX_CHAN       (1)
#define UART2_DMA_TX_CHAN       (2)
#define UART2_DMA_RX_CHAN       (3)

/* timer clk  fpga 1M,soc 50M*/
#define TIMER_CLK			(1000000)

/*sdio*/
#define SIMPLE_0     (0)
#define SIMPLE_90    (4)
#define SIMPLE_180   (8)
#define SIMPLE_270   (12)


#define SDIO0_RST_BIT       (~UL(1<<2))
#define SDIO0_CLK_RATE      (50000000)
#define SDIO0_CLK_DRV_SHIFT (20)
#define SDIO0_CLK_DRV_DEGREE (SIMPLE_180)
#define SDIO0_CLK_SAM_SHIFT (16)
#define SDIO0_CLK_SAM_DEGREE (SIMPLE_0)


#define SDIO1_RST_BIT       (~UL(1<<1))
#define SDIO1_CLK_RATE      (50000000)
#define SDIO1_CLK_DRV_SHIFT (12)
#define SDIO1_CLK_DRV_DEGREE (SIMPLE_180)
#define SDIO1_CLK_SAM_SHIFT (8)
#define SDIO1_CLK_SAM_DEGREE (SIMPLE_0)

#define SDC0_HRSTN  (0x1<<2)
#define SDC1_HRSTN  (0x1<<1)
#define SDC2_HRSTN  (0)


/*usb*/
#define USB_TUNE_ADJ_SET	(0x78203344)


#define CLK_SCAN_BIT_POS                (28)
#define INSIDE_PHY_ENABLE_BIT_POS       (24)
#define MAC_REF_CLK_DIV_MASK            (0x0f)
#define MAC_REF_CLK_DIV_BIT_POS         (24)
#define MAC_PAD_RMII_CLK_MASK           (0x0f)
#define MAC_PAD_RMII_CLK_BIT_POS        (24)
#define MAC_PAD_MAC_REF_CLK_BIT_POS     (28)
#define ETH_REF_CLK_OUT_GATE_BIT_POS    (25)
#define ETH_RMII_CLK_OUT_GATE_BIT_POS   (28)
#define IN_OR_OUT_PHY_SEL_BIT_POS       (26)
#define INSIDE_CLK_GATE_BIT_POS         (0)
#define INSIDE_PHY_SHUTDOWN_BIT_POS     (31)
#define INSIDE_PHY_RST_BIT_POS          (30)
#define INSIDE_PHY_TRAINING_BIT_POS     (27)
#define INSIDE_PHY_TRAINING_MASK        (0x0f)

#define TRAINING_EFUSE_ACTIVE_BIT_POS          4

#define I2S_CLK_FREQ		450000000 /* 450M */

#endif /* __ASM_ARCH_WS_H */
